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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 1/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology features general description block diagram ? ieee802.3 and ieee802.3u compliant. ? provide 16 rmii (reduced media independent interface) ports. ? programmable 1k/8k mac addresses filtering database. ? store and forward switching function and bad packet filtering function. ? optional back_pressure/802.3x flow control/ flooding control/broadcast control. ? optional eeprom interface for advanced switch configurations. ? 4mb/2mb packet buffer with sgram/sdram flexible memory interface. ? port vlan/trunking. ? link/rx activity, packet buffer utilization led display. ? 83mhz for non-blocking 16 port switch. ? build in internal/external memory test function. ? 208 pin pqfp package, 3.3v operation volt- age. 16 port 10m/100m ethernet switch the MTD516 complies fully with the ieee802.3, 802.3u and 802.3x specifications and is a non-blocking 16 port 10m/100m ethernet switch device. support 16 rmii ports for 10m/100m oper- ation. 4mb memory interface provides maximum 2730 packet buffers for ethernet packet buffering. up to 8192 address entrys are provided by the MTD516, and the MTD516 use full ethernet address compare algorithm to minimize hashing collision events. the MTD516 provides eeprom interface to config port trunking, port vlan, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. each MTD516 ports support 10m/100m auto-negotiation by mii man- agement interface. the MTD516 also provides 2 pins for link/ rx activity, packet buffer utilization led display function. sdram/ rmii15 port switch logic mac15 dma15 rmii12 mac4 dma4 rmii13 mac13 dma13 rmii14 mac14 dma14 rmii3 mac3 dma3 rmii0 mac0 dma0 rmii1 mac1 dma1 rmii2 mac2 dma2 memory arbiter memory controller sgram interface 3~12
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 2/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology system diagram MTD516 octal physceiver octal physceiver rmii0-7 rmii11-15 octal transformer octal transformer rj45 rj45 eeprom leds sgram (256kx32x2) sgram (512kx32x2) (**option) (**programmable) mii management
3/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 1.0 pin connection 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 1 5 6 1 5 5 1 5 4 1 5 3 1 5 2 1 5 1 1 5 0 1 4 9 1 4 8 1 4 7 1 4 6 1 4 5 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 dq42 dq41 dq40 dq32 dq33 dq34 dq35 dq36 dq37 vcc gnd dq38 dq39 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 vcc sysclk gnd rxd15_1 rxd15_0 crsdv15 txen15 txd15_0 txd15_1 rxd14_1 rxd14_0 crsdv14 txen14 txd14_0 txd14_1 vcc gnd rxd13_1 rxd13_0 crsdv13 txen13 txd13_0 txd13_1 rxd12_1 rxd12_0 crsdv12 txen12 txd12_0 txd12_1 rxd11_1 rxd11_0 d q 9 d q 8 d q 0 d q 1 d q 2 d q 3 d q 4 d q 5 d q 6 d q 7 d q 1 6 d q 1 7 d q 1 8 d q 1 9 d q 2 0 v c c g n d d q 2 1 d q 2 2 d q 2 3 w e b c a s b r a s b c s 0 b b a a d 0 a d 1 a d 2 a d 3 a d 4 a d 5 a d 6 a d 7 a d 8 v c c m e m c l k g n d d q 6 3 d q 6 2 d q 6 1 d q 6 0 d q 5 9 d q 5 8 d q 5 7 d q 5 6 d q 4 7 d q 4 6 d q 4 5 d q 4 4 v c c g n d d q 4 3 t x d 4 _ 1 t x d 4 _ 0 t x e n 4 c r s d v 4 r x d 4 _ 0 r x d 4 _ 1 t x d 5 _ 1 t x d 5 _ 0 t x e n 5 g n d v c c c r s d v 5 r x d 5 _ 0 r x d 5 _ 1 t x d 6 _ 1 t x d 6 _ 0 t x e n 6 c r s d v 6 r x d 6 _ 0 r x d 6 _ 1 t x d 7 _ 1 t x d 7 _ 0 t x e n 7 c r s d v 7 r x d 7 _ 0 r x d 7 _ 1 g n d v c c t x d 8 _ 1 t x d 8 _ 0 t x e n 8 c r s d v 8 r x d 8 _ 0 r x d 8 _ 1 t x d 9 _ 1 t x d 9 _ 0 t x e n 9 c r s d v 9 r x d 9 _ 0 r x d 9 _ 1 g n d v c c t x d 1 0 _ 1 t x d 1 0 _ 0 t x e n 1 0 c r s d v 1 0 r x d 1 0 _ 0 r x d 1 0 _ 1 t x d 1 1 _ 1 t x d 1 1 _ 0 t x e n 1 1 c r s d v 1 1 MTD516 dq10 dq11 gnd vcc dq12 dq13 dq14 dq15 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 leddata ledclk eedata eeclk gnd refclk vcc resetb mdc mdio txd0_1 txd0_0 txen0 crsdv0 rxd0_0 rxd0_1 gnd vcc txd1_1 txd1_0 txen1 crsdv1 rxd1_0 rxd1_1 txd2_1 txd2_0 txen2 crsdv2 rxd2_0 rxd2_1 txd3_1 txd3_0 txen3 crsdv3 rxd3_0 rxd3_1
4/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 2.0 pin descriptions rmii port interface pins name pin number i/o descriptions crsdv0 186 i port0 rmii receive interface signal, crsdv0 is asserted high when port0 media is non_idle. rxd0_0 rxd0_1 187 188 i i port0 rmii receive data bit_0. port0 rmii receive data bit_1. txen0 185 o port0 rmii transmit enable signal. txd0_0 txd0_1 184 183 o o port0 rmii transmit data bit_0. port0 rmii transmit data bit_1. crsdv1 194 i port1 rmii receive interface signal, crsdv1 is asserted high when port1 media is non_idle. rxd1_0 rxd1_1 195 196 i i port1 rmii receive data bit_0. port1 rmii receive data bit_1. txen1 193 o port1 rmii transmit enable signal. txd1_0 txd1_1 192 191 o o port1 rmii transmit data bit_0. port1 rmii transmit data bit_1. crsdv2 200 i port2 rmii receive interface signal, crsdv2 is asserted high when port2 media is non_idle. rxd2_0 rxd2_1 201 202 i i port2 rmii receive data bit_0. port2 rmii receive data bit_1. txen2 199 o port2 rmii transmit enable signal. txd2_0 txd2_1 198 197 o o port2 rmii transmit data bit_0. port2 rmii transmit data bit_1. crsdv3 206 i port3 rmii receive interface signal, crsdv0 is asserted high when port3 media is non_idle. rxd3_0 rxd3_1 207 208 i i port3 rmii receive data bit_0. port3 rmii receive data bit_1. txen3 205 o port3 rmii transmit enable signal. txd3_0 txd3_1 204 203 o o port3 rmii transmit data bit_0. port3 rmii transmit data bit_1. crsdv4 4 i port4 rmii/mii receive interface signal, crsdv4 is asserted high when port4 media is non_idle. rxd4_0 rxd4_1 5 6 i i port4 rmii/mii receive data bit_0. port4 rmii/mii receive data bit_1. txen4 3 o port4 rmii transmit enable signal txd4_0 txd4_1 2 1 o o port4 rmii/mii transmit data bit_0. port4 rmii/mii transmit data bit_1. crsdv5 12 i port5 rmii receive interface signal, crsdv5 is asserted high when port5 media is non_idle. rxd5_0 rxd5_1 13 14 i i port5 rmii receive data bit_0. port5 rmii receive data bit_1. txen5 9 o port5 rmii transmit enable signal. txd5_0 txd5_1 8 7 o o port5 rmii transmit data bit_0. port5 rmii transmit data bit_1.
5/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology crsdv6 18 i port6 rmii receive interface signal, crsdv6 is asserted high when port6 media is non_idle. rxd6_0 rxd6_1 19 20 i i port6 rmii receive data bit_0. port6 rmii receive data bit_1. txen6 17 o port6 rmii transmit enable signal. txd6_0 txd6_1 16 15 o o port6 rmii transmit data bit_0. port6 rmii transmit data bit_1. crsdv7 24 i port7 rmii receive interface signal, crsdv7 is asserted high when port7 media is non_idle. rxd7_0 rxd7_1 25 26 i i port7 rmii receive data bit_0. port7 rmii receive data bit_1. txen7 23 o port7 rmii transmit enable signal. txd7_0 txd7_1 22 21 o o port7 rmii transmit data bit_0. port7 rmii transmit data bit_1. crsdv8 32 i port8 rmii receive interface signal, crsdv8 is asserted high when port8 media is non_idle. rxd8_0 rxd8_1 33 34 i i port8 rmii receive data bit_0. port8 rmii receive data bit_1. txen8 31 o port8 rmii transmit enable signal. txd8_0 txd8_1 30 29 o o port8 rmii transmit data bit_0. port8 rmii transmit data bit_1. crsdv9 38 i port9 rmii receive interface signal, crsdv9 is asserted high when port9 media is non_idle. rxd9_0 rxd9_1 39 40 i i port9 rmii receive data bit_0. port9 rmii receive data bit_1. txen9 37 o port9 rmii transmit enable signal. txd9_0 txd9_1 36 35 o o port9 rmii transmit data bit_0. port9 rmii transmit data bit_1. crsdv10 46 i port10 rmii receive interface signal, crsdv10 is asserted high when port10 media is non_idle. rxd10_0 rxd10_1 47 48 i i port10 rmii receive data bit_0. port10 rmii receive data bit_1. txen10 45 o port10 rmii transmit enable signal. txd10_0 txd10_1 44 43 o o port10 rmii transmit data bit_0. port10 rmii transmit data bit_1. crsdv11 52 i port11 rmii receive interface signal, crsdv11 is asserted high when port11 media is non_idle. rxd11_0 rxd11_1 53 54 i i port11 rmii receive data bit_0. port11 rmii receive data bit_1. txen11 51 o port11 rmii transmit enable signal. txd11_0 txd11_1 50 49 o o port11 rmii transmit data bit_0. port11 rmii transmit data bit_1. rmii port interface pins name pin number i/o descriptions
6/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology crsdv12 58 i port12 rmii receive interface signal, crsdv12 is asserted high when port12 media is non_idle. rxd12_0 rxd12_1 59 60 i i port12 rmii receive data bit_0. port12 rmii receive data bit_1. txen12 57 o port12 rmii transmit enable signal. txd12_0 txd12_1 56 55 o o port12 rmii transmit data bit_0. port12 rmii transmit data bit_1. crsdv13 64 i port13 rmii receive interface signal, crsdv13 is asserted high when port13 media is non_idle. rxd13_0 rxd13_1 65 66 i i port13 rmii receive data bit_0. port13 rmii receive data bit_1. txen13 63 o port13 rmii transmit enable signal. txd13_0 txd13_1 62 61 o o port13 rmii transmit data bit_0. port13 rmii transmit data bit_1. crsdv14 72 i port14 rmii receive interface signal, crsdv14 is asserted high when port14 media is non_idle. rxd14_0 rxd14_1 73 74 i i port14 rmii receive data bit_0. port14 rmii receive data bit_1. txen14 71 o port14 rmii transmit enable signal. txd14_0 txd14_1 70 69 o o port14 rmii transmit data bit_0. port14 rmii transmit data bit_1. crsdv15 78 i port15 rmii receive interface signal, crsdv15 is asserted high when port15 media is non_idle. rxd15_0 rxd15_1 79 80 i i port15 rmii receive data bit_0. port15 rmii receive data bit_1. txen15 77 o port15 rmii transmit enable signal. txd15_0 txd15_1 76 75 o o port15 rmii transmit data bit_0. port15 rmii transmit data bit_1. rmii port interface pins name pin number i/o descriptions
7/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology note: sgram/sdram access time: 10 ns (max) synchronous dram/gram interface pins name pin number i/o descriptions ad[8:0] 123~131 o memory row/column address bus outputs ad[7:0] are row/column address [7:0]. ad[8] : this pin should connect to sgram/sdram msb address bit. dq[63:0] 119~112, 84~91, 111~108, 105~102, 92~93, 96~101, 172~165, 137~139, 142~146, 164~161, 158~155, 147~154 i/o memory data bus dq[63:56] : 119~112 dq[55:48] : 84~91 dq[47:44] : 111~108 dq[43:40] : 105~102 dq[39:38] : 92~93 dq[37:32] : 96~101 dq[31:24] : 172~165 dq[23:21] : 137~139 dq[20:16] : 142~146 dq[15:12] : 164~161 dq[11:8] : 158~155 dq[7:0] : 147~154 rasb 134 o sgram/sdram row address select casb 135 o sgram/sdram column address select web 136 o sgram/sdram write enable ba 132 o sgram/sdram bank select cs0b 133 o memory chip select 0 memclk 121 o memory clock output. miscellaneous pins name pin number i/o descriptions resetb 180 i system reset input, low active. sysclk 82 i switch core system clock input refclk 178 i rmii reference clock input mdc 181 i/o mii management clock inout. mdio 182 i/o mii management data inout eeclk/ sdc 176 i/o after resetb deassert to ? ms , this pin indicate eeclk, after 150 ms, it indicate sdc. eedata/ sdio 175 i/o after resetb deassert to ? ms , this pin be indicated eedata, after 150 ms, it indicate sdio. ledclk 174 i/o led clock. using bursted clock for latching 32 display informations (one clock latch one information) , per burst have 32 continuous clocks (clock period = 320 ns); and the time between burst to burst is 655 us.
8/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology leddata 173 i/o led data (high_active). the serial output display informations using bursted styling ,per burst have 32 informations, as following: ledclk leddata ledclk leddata 01 p0_rxact 17 uti_1% 02 p1_rxact 18 uti_3% 03 p2_rxact 19 uti_5% 04 p3_rxact 20 uti_10% 05 p4_rxact 21 uti_15% 06 p5_rxact 22 uti_20% 07 p6_rxact 23 uti_30% 08 p7_rxact 24 uti_35% 09 p8_rxact 25 uti_40% 10 p9_rxact 26 uti_50% 11 p10_rxact 27 uti_60% 12 p11_rxact 28 uti_70% 13 p12_rxact 29 uti_80% 14 p13_rxact 30 uti_90% 15 p14_rxact 31 bufferalarm 16 p15_rxact 32 memtestfail vcc 11,28,42,68, 83,95,107, 122,141,160, 179,190, pwr power pins gnd 10,27,41,67, 81,94,106, 120,140,159, 177,189, gnd ground pins miscellaneous pins name pin number i/o descriptions
9/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 3.0 power on setting configuration jumper configuration after power on reset pin name function defa ult descriptions mdc flowctrlen 1 802.3x flow control function enable. external pull_hgih =1, 802.3x flow control enable. external pull_low = 0, 802.3x flow control disable. eeclk bakpsureen 1 in half duplex mode, backpressure function enable. external pull_hgih =1, backpressure enable. external pull_low = 0, backpressure disable. eedata miipollen 1 polling phy device?s mii register function enable. external pull_hgih =1, phy auto polling enable. external pull_low = 0, phy auto polling disable. ledclk agingen 1 aging out function for address learning enable. external pull_hgih =1, aging out function enable. external pull_low = 0, aging out function disable. leddata bisten 1 embbeded memory self-test function enable. external pull_hgih =1, memory bist enable. external pull_low = 0, memory bist disable. txen13 fastmode 0 for chip test only. external pull_hgih =1, chip fast test mode enable. external pull_low = 0, chip fast test mode disable. txen12 scanmode 0 for chip test only. external pull_hgih =1, chip scan test mode enable. external pull_low = 0, chip scan test mode disable. txen11 8kaddrtblen 0 8k entry address table enable. external pull_hgih =1, 8k address table enable. external pull_low = 0, 8k address table disable; defaule is 1k entry. txen10 eepromen 0 auto_load from eeprom function enable. external pull_hgih =1, auto load from eeprom function enable. external pull_low = 0, auto load from eeprom function disable. txen9 broadstor- men 0 broadcast storm protect function enable. external pull_hgih =1, broadcast storm protection enable. external pull_low = 0, broadcast storm protection disable. txen8 en12portsw 0 for 12 port switch, only port11~port0 enable. external pull_hgih =1, 12 port switch enable. external pull_low = 0, default is 16 port switch. txen7 p15fxen 0 port 15 fx function indicator. external pull_hgih =1, port15 fx function enable. external pull_low = 0, port15 fx function disable.
10/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology txen6 p15full 0 port15 duplex ability indicator (under port15 configured in fx mode). external pull_hgih =1, port15 operate in full_duplex mode. external pull_low = 0, port15 operate in half_duplex mode. txen5 en1522 0 vlan tag 1522 bytes acceptance function enable. external pull_hgih =1, vlan tag 1522 bytes acceptance enable. external pull_low = 0, vlan tag 1522 bytes acceptance enable disable. txen4 floodctrlen 0 flooding control function enable. external pull_hgih =1, flooding control function enable. external pull_low = 0, flooding control function disable. txen3 floodid[3] 0 flooding port id bit 3 external pull_hgih =1. external pull_low = 0. txen2 floodid[2] 0 flooding port id bit 2 external pull_hgih =1. external pull_low = 0. txen1 floodid[1] 0 flooding port id bit 1 external pull_hgih =1. external pull_low = 0. txen0 floodid[0] 0 flooding port id bit 0 external pull_hgih =1. external pull_low = 0. jumper configuration after power on reset pin name function defa ult descriptions
11/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 4.0 functional descriptions the MTD516 is an 16 ports 10/100 mbps fast ethernet switch controller. it is a low cost solution for six- teen ports fast ethernet soho switch design. no cpu interface is required; after power on reset, MTD516 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device, and MTD516 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc func- tions. the following descriptions are MTD516?s major functional blocks overview. 4.1 packet store and forwarding the MTD516 use simple store and forward algorithm as packet switching method. input packet from ports will be stored to external memory first, while packet is good for forward (crc chech ok, 64bytes < length < 1518bytes, not local packets, in the same vlan group ) , if this packet?s da hits, than forward this packet to the destination port, otherwise this packet will be broadcasted. 4.2 learning and routing the MTD516 supports 1k or 8k mac entries for switching. dynamic address learning is performed by each good unicast packet is completely received. the static address learning is achieved by eeprom configuration. on the other hand, the routing process is performed whenever the packet?s da is cap- tured. if the da can not get a hit result, the packet is going to switch broadcast or forward to the dedi- cated port according to the flooding control selction. 4.3 aging only the dynamic address entries are scheduled in the aging machine. if one station does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time can be program through the eeprom auto load configuration. (default value is 300 seconds) 4.4 buffer queue management the buffer queue manager is implemented to manage the external shared memory (use sdram/ sgram) for packet buffering. the main function of the buffer queue manager is to maintain the linked list consists of buffer ids, which is used to show the corresponding memory address for each incoming packet. in addition, the buffer queue manager monitors the rested free spaces status of the external memory, if the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission id queue overflow happening. MTD516 provide 802.3x flow control in full duplex mode and back pressure control in half duplex mode. 4.5 full duplex 802.3x flow control in full duplex mode, MTD516 supports the standard flow control defined in ieee802.3x standard. it enables the stopping of remote node transmissions via a pause frame information interactoin. when the ?802.3x flow control enable? bit is setted during power on reset (mdc pin is external pull_high), it enables MTD516 supporting 802.3x flow control function in full_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value(recommended xon_th = 40?h under total free id less then 100?h), MTD516 will send out a pause packet with pause time equal to fff to stop the remote node transmission; when the output port buffer queue?s on_using value reduce to the initialization threshold value(recommended xoff_th = 1c?h when using 2mbytes external mem- ory), MTD516 will also send a pause packet with pause time equal to zero to inform the remote node to retransmit packet. 4.6 half duplex back pressure control in half duplex mode, MTD516 provide a back pressure control mechanism to avoid dropping packets during network conjection situation. when the ?back pressure control enable? bit is set during power on
12/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology reset (eeclk pin is external pull_high), it enables MTD516 supporting back pressure function in half_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value (same with the xon_th value), MTD516 will send a jam pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. if the ?back pressure control enable? bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. 4.7 mii polling the MTD516 supports phy management through the serial mdio/mdc interface. after power on reset, the MTD516 write related abilities to the advertisement register 4 of connected phy devices and restart the auto_negotiation prcedure via mdio/mdc interface using the predefined phy addresses increasingly from ?01000?b to ?10111?b. the MTD516 will periodically and continuously poll and update the link status and link partner?s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected phy devices through mdio/mdc serial interface. 4.8 mac and dma engine the MTD516?s mac performs all the functions in ieee802.3 protocol, such as frame formatting, frame stripping, crc checking, bad packet dropping, defering to line traffic, and collision handling. the mac rx_engine checks incoming packets and drops the bad packet which include crc error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the ?vlan tag 1522 bytes receive enable? bit is set during power on reset). before transmission, the mac tx_engine will constantly monitor the line traffic using derfering precedure. only if it has been idle for a 96 bits time (a minimum interpacket gap time, ipg time), actual transmmission can be started. for the half duplex mode, mac engine will detect collision; if a collision is detected, the mac tx_engine will transmit a jam pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (MTD516 implements the truncated exponential back_off algorithm defined in ieee 802.3 standard). for the full duplex mode, collision signal is ignored. the MTD516?s dma engine performs the packets non_blocking transportation between mac engine and external memory according to a high speed switching procedure. the switching procedure is com- pleted by address learning/routing process and buffer queue management operation. 4.9 eeprom interface MTD516 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device(24c02) after power on reset . MTD516 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc functions. 4.10 port based vlan the MTD516 supports vlan configuration by port based methodology. one port select the certain ports to form its vlan group by configuring the vlan register. the packet (including broadcast packet) is not forwarding to the destination port whose vlan group is different from the source port. 4.11 port trunking the port trunking function can also be implemented by vlan registers. one trunk port isolates the packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology. the non-trunk port should choose only one trunk port for transmitting, which can achieve the load bal- ancing and maintain the packet sequences. 4.12 memory interface two kinds of external memory interface can be selected by user -- 2m byte memory (256k32 x 2) and 4 m bytes ( 512k32 x 2). maximum 4m byte external memory can be used for packet buffering. ?-10 ?
13/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology speed grade of sgram/sdram device is recommanded. the following table is the sgram applica- tion pin connection : 4.13 internal mii registers acess and control the MTD516 support 2 serial pins (sdio/sdc) for internal registers acess and control; the detailed registers informations are presented in section5.0 (internal mii registers). 4.14 led display the MTD516 use 2 pins to output 2 kinds of led display -- leddata, ledclk, using ledclk rising edge with 32 bits shift register to latch leddata as data[31:0]. data[15:0] report port15~0 link/receive activity led status. data[29:16] report packet buffer utilization rating, and data[31] report external memory test result(after power reset, MTD516 will test external sdram auto- matically), data[30] report the buffer almost full alarm signal . memory type memory chip no a[8] gnd 256k32 x 2 a8 - 512k32 x 2 a9 a8
14/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 5.0 register description global register : control register (addr = 5?h0) bit name r/w descriptions 0 port reg select enable r/w ?1? means reg addr1-4 as port registers described as follows. ?0? means reg addr1-4 as global registers described as follows. 4-1 port reg select r/w if bit0 = 0, bit[4:1] don?t care, and under bit[0] = 1, bit[4:1] = 0, reg1-4 switch to port0 registers bit[4:1] = 1, reg1-4 switch to port1 registers bit[4:1] = 2, reg1-4 switch to port2 registers bit[4:1] = 3, reg1-4 switch to port3 registers bit[4:1] = 4, reg1-4 switch to port4 registers bit[4:1] = 5, reg1-4 switch to port5 registers bit[4:1] = 6, reg1-4 switch to port6 registers bit[4:1] = 7, reg1-4 switch to port7 registers bit[4:1] = 8, reg1-4 switch to port8 registers bit[4:1] = 9, reg1-4 switch to port9 registers bit[4:1] = a, reg1-4 switch to port10 registers bit[4:1] = b, reg1-4 switch to port11 registers bit[4:1] = c, reg1-4 switch to port12 registers bit[4:1] = d, reg1-4 switch to port13 registers bit[4:1] = e, reg1-4 switch to port14 registers bit[4:1] = f, reg1-4 switch to port15 registers 5 scan mode enable r/w ?1? enable ?0? disable 9-6 scanout group select r/w bit[9:6]= 0 means group 0 , etc ... 13-10 scanout port select r/w bit[13:10] = 0 means port0, etc,... 15-14 reserved 15-0 default value 16?h0000 global register : xon/xoff register (addr = 5?h1) bit name r/w descriptions 7-0 xonth r/w xon threshold 15-8 xoffth r/w xoff threshold 15-0 default value xon threshold default is 8?d64(2m) xoff threshold default is 8?h28(2m) p.s while eeprom is enabled, this register?s content will be updated by eeprom.
15/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology global register : aging register (addr = 5?h2) bit name r/w descriptions 15-0 ageth r/w aging time. 15-0 default value default is 16?d300. p.s while eeprom is enabled, this register?s content will be updated by eeprom. global register : uplink0 register (addr = 5?h3) bit name r/w descriptions 15 reserved 14-0 port2 id r/w specify port2?s uplink port id 9-5 port1 id r/w specify port1?s uplink port id 4-0 port0 id r/w specify port0?s uplink port id 15-0 default value default is 16?h001f. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command. global register : uplink1 register (addr = 5?h4) bit name r/w descriptions 15 reserved 14-0 port5 id r/w specify port5?s uplink port id 9-5 port4 id r/w specify port4?s uplink port id 4-0 port3 id r/w specify port3?s uplink port id 15-0 default value default is 16?h0000. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command. global register : uplink2 register (addr = 5?h5) bit name r/w descriptions 15 reserved 14-0 port8 id r/w specify port8?s uplink port id 9-5 port7 id r/w specify port7?s uplink port id 4-0 port6 id r/w specify port6?s uplink port id 15-0 default value default is 16?h0000. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command.
16/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology global register : uplink3 register (addr = 5?h6) bit name r/w descriptions 15 reserved 14-0 port11 id r/w specify port11?s uplink port id 9-5 port10 id r/w specify port10?s uplink port id 4-0 port9 id r/w specify port9?s uplink port id 15-0 default value default is 16?h0000. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command. global register : uplink4 register (addr = 5?h7) bit name r/w descriptions 15 reserved 14-0 port14 id r/w specify port14?s uplink port id 9-5 port13 id r/w specify port13?s uplink port id 4-0 port12 id r/w specify port12?s uplink port id 15-0 default value default is 16?h0000. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command. global register : uplink5 register (addr = 5?h8) bit name r/w descriptions 15-5 reserved 4-0 port15 id r/w specify port15?s uplink port id 15-0 default value default is 16?h0000. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command. global register : brdcast storm threshold register (addr = 5?h9) bit name r/w descriptions 15-9 reserved 8 r/w backpressure enhance mode enable. 7-0 brdcast th r/w specify broadcast storm threshold 15-0 default value default is 16?h00ff. p.s this register?s writing sequence is jumper setting ==> eeprom ==>mii management command.
17/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology global register : status0 register (addr = 5?ha) bit name r/w descriptions 15-0 fifofull r/o output port15-0 rxdma fifofull signal global register : status1 register (addr = 5?hb) bit name r/w descriptions 15-0 fifoempty r/o output port15-0 txdma tpur(fifoempty)signal global register : status2 register (addr = 5?hc) bit name r/w descriptions 15-14 r/o reserved 13 r/o reserved 12 r/o reserved 11 r/o reserved 10 freecntis0 r/o freecntis0 9 eedone r/o eedone 8 membisterr r/o sgram bist error 7 membistdone r/o sgram bist done 6 lthtblbisterr r/o length table bist error 5 lthtblbistdone r/o length table bist done 4 addrtblbisterr r/o internal 1k address table bist error 3 addtblbist- done r/o internal 1k address table bist done 2 bufinitdone r/o buffer link initialization done 1 bufbisterr r/o buffer table bist error 0 bufbistdone r/o buffer table bist done global register : control/status0 register (addr = 5?hd) bit name r/w descriptions 15-0 flowctrl r/w output mii polling port15-0 flow control information. p.s ?1? means flow control is enabled 15-0 default value when polling disabled, default value is 16?hffff when polling enabled, default value is 16?h0000.
18/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology global register : control/status1 register (addr = 5?he) bit name r/w descriptions 15-0 link r/w output mii polling port15-0 link information. p.s ?1? means link good 15-0 default value when polling disabled, default value is 16?hffff when polling enabled, default value is 16?h0000. global register : control/status2 register (addr = 5?hf) bit name r/w descriptions 15-0 speed r/w output mii polling port15-0 speed information. p.s ?1? means 100m 15-0 default value when polling disabled, default value is 16?hffff when polling enabled, default value is 16?h0000. global register : control/status3 register (addr = 5?h10) bit name r/w descriptions 15-0 fullduplex r/w output mii polling port15-0 full duplex information. p.s ?1? means full duplex 15-0 default value when polling disabled, default value is 16?hffff when polling enabled, default value is 16?h0000. global register : debugreg0 register (addr = 5?h11) bit name r/w descriptions 15-0 localfilter r/w ?1? disable port15-0 local packet filter function. 15-0 default value default is 16?h0000 global register : debugreg1 register (addr = 5?h12) bit name r/w descriptions 15-0 rxlengthchk r/w ?1? disable port15-0 rx length check function. 15-0 default value default is 16?h0000
19/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology global register : debugreg2 register (addr = 5?h13) bit name r/w descriptions 15-0 reserved r/w reserved 15-0 default value default is 16?h0000 global register : debugreg3 register (addr = 5?h14) bit name r/w descriptions 15-0 crcchk r/w ?1? disable port15-0 crc check function. 15-0 default value default is 16?h0000 global register : debugreg4 register (addr = 5?h15) bit name r/w descriptions 15-0 random# r/w ?1? fix port15-0 random backoff number. 15-0 default value default is 16?h0000 global register : debugreg5 register (addr = 5?h16) bit name r/w descriptions 15-0 reserved r/w reserved 15-0 default value default is 16?h0000 global register : freehead register (addr = 5?h17) bit name r/w descriptions 15-12 reserved. 11-0 freehead r/o output free list head id global register : freetail register (addr = 5?h18) bit name r/w descriptions 15-12 reserved. 11-0 freetail r/o output free list tail id global register : freecnt register (addr = 5?h19) bit name r/w descriptions 15-12 reserved. 11-0 freecnt r/o output free list count value.
20/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 6.0 eeprom content global register : portenable register (addr = 5?h1a) bit name r/w descriptions 15-0 portenable r/w ?1? disable port 15-0 15-0 default default value is 16?h0000 port register : txlinkhead register (addr = 5?h1) bit name r/w descriptions 15-13 reserved 12-0 txlinkhead r/o output port tx queue head value port register : txlinkhead register (addr = 5?h2) bit name r/w descriptions 15-13 reserved 12-0 txlinkcnt r/o output port tx queue count value port register : vlanreg register (addr = 5?h3) bit name r/w descriptions 15-0 vlanreg r/w select port vlan group. eeprom content addr name descriptions h0 eob last eeprom content address value h1 agelow age time bit 7-0. h2 agehigh age time bit 15-8. h3 vlan0l port0 vlan low byte register. h4 vlan0h port0 vlan low byte register. h5 vlan1l port1 vlan low byte register. h6 vlan1h port1 vlan low byte register. h7 vlan2l port2 vlan low byte register.
21/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology h8 vlan2h port2 vlan low byte register. h9 vlan3l port3 vlan low byte register. ha vlan3h port3 vlan low byte register. hb vlan4l port4 vlan low byte register. hc vlan4h port4 vlan low byte register. hd vlan5l port5 vlan low byte register. he vlan5h port5 vlan low byte register. hf vlan6l port6 vlan low byte register. h10 vlan6h port6 vlan low byte register. h11 vlan7l port7 vlan low byte register. h12 vlan7h port7 vlan low byte register. h13 vlan8l port8 vlan low byte register. h14 vlan8h port8 vlan low byte register. h15 vlan9l port9 vlan low byte register. h16 vlan9h port9 vlan low byte register. h17 vlan10l port10 vlan low byte register. h18 vlan10h port10 vlan low byte register. h19 vlan11l port11 vlan low byte register. h1a vlan11h port11 vlan low byte register. h1b vlan12l port12 vlan low byte register. h1c vlan12h port12 vlan low byte register. h1d vlan13l port13 vlan low byte register. h1e vlan13h port13 vlan low byte register. h1f vlan14l port14 vlan low byte register. h20 vlan14h port14 vlan low byte register. h21 vlan15l port15 vlan low byte register. h22 vlan15h port15 vlan low byte register. h23 uplink0 [4:0] port 0 flooding port. [7:5] reserved. h24 uplink1 [4:0] port 1 flooding port. [7:5] reserved. h25 uplink2 [4:0] port 2 flooding port. [7:5] reserved. h26 uplink3 [4:0] port 3 flooding port. [7:5] reserved. h27 uplink4 [4:0] port 4 flooding port. [7:5] reserved. h28 uplink5 [4:0] port 5 flooding port. [7:5] reserved. h29 uplink6 [4:0] port 6 flooding port. [7:5] reserved. h2a uplink7 [4:0] port 7 flooding port. [7:5] reserved. h2b uplink8 [4:0] port 8 flooding port. [7:5] reserved. h2c uplink9 [4:0] port 9 flooding port. [7:5] reserved. h2d uplink10 [4:0] port 10 flooding port. [7:5] reserved. h2e uplink11 [4:0] port 11 flooding port. [7:5] reserved. h2f uplink12 [4:0] port 12 flooding port. [7:5] reserved. h30 uplink13 [4:0] port 13 flooding port. [7:5] reserved. h31 uplink14 [4:0] port 14 flooding port. [7:5] reserved. h32 uplink15 [4:0] port 15 flooding port. [7:5] reserved. eeprom content addr name descriptions
22/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology h33 brdcastth broadcast threshold h34 xonth xon threshold h35 xoffth xoff threshold h36 disportl disable port 7-0 h37 disporth disable port 15-8 h38 ctrlenable system control byte bit0-- enhance backpressure enable [7:1] reserved. h39- h3f reserved h40- h46 staticsa1 45[7:0]~40[7:0] means static sa[47:0], 46[3:0] means port id, 46[7:4] reserved. h47- h4d staticsa2 4c[7:0]~47[7:0] means static sa[47:0], 47[3:0] means port id, 47[7:4] reserved. eeprom content addr name descriptions
23/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 7.0 electrical characteristics 7.1 absolute maximum ratings 7.2 recommended operating conditions 7.3 dc electrical characteristics (under recommended operating conditions and vcc = 3.0 ~ 3.6v, tj = 0 to +115 o c) symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - vcc v t j commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-direction buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 0.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 2.4 v r i input pull-up/down resistance v il =0v or v ih =v cc 75 kohm
24/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 7.4 electrical characteristics symbol parameter min. typ. max. unit note t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns symbol parameter min. typ. max. unit note t5 memory clock cycle 12 ns t6 memory command/address/data setup time 6 ns t7 memory command/address/data hold time 2 ns t8 row active to burst write 2 clk figure 1. rmii timing refclk crsdv txen txd[1:0] rxd[1:0] t1 t2 t3 t4 valid valid figure 2. memory write timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[63:0] valid t6 t7 t8 web memclk t6 t7 t6 t7
25/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology symbol parameter min. typ. max. unit note t10 memory read data setup time 2 ns t11 memory ead data hold time 2 ns symbol parameter min. typ. max. unit note t11 eeprom clock cycle 10 us t12 eedata input setup time 1 ns t13 eedata input hold time 1 ns figure 3. memory read timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[63:0] valid t6 t7 t8 web memclk t6 t7 t9 t10 figure 4. eeprom timing eeclk t11 t13 eedata valid t12
26/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology symbol parameter min. typ. max. unit note t14 led display strobe period 20 us t15 ledclk setup time 5 us t16 ledclk hold time 5 us figure 5. led interface ledclk t16 leddata valid t15 valid valid t14
27/27 MTD516 revision 1.2 19/06/2000 MTD516 (preliminary) myson technology 8.0 208 pin pqfp package data 1 52 53 104 105 156 157 208 seating plane see detail a e b d d1 e e 1 l 0.25mm detail sym- bol dimension in mm dimension in inch min norm max min norm max a - - 4.10 - - 0.161 a1 0.25 - - 0.010 - - a2 3.20 3.32 3.60 0.126 0.131 0.142 d 30.60 bsc 1.205 bsc d1 28.00 bsc 1.102 bsc d2 25.50 1.004 e 30.60 bsc 12.05 bsc e1 28.00 bsc 1.102 bsc e2 25.50 1.004 r2 0.08 - 0.25 0.003 - 0.010 r1 0.08 - - 0.003 - - 0 o 3.5 o 7 o 0 o 3.5 o 7 o 0 o - - 0 o - - 8 o ref 8 o ref 8 o ref 8 o ref c 0.09 0.15 0.20 0.004 0.006 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 ref 0.052 ref s 0.20 - - 0.008 - - e 0.50 bsc 0.020 bsc b 0.17 0.20 0.27 0.007 0.008 0.011 y e 2 d2 4x aaa|c|a-b|o bbb|h|a-b|o o|ddd m |c|a-b s |d s 1 -c- |ccc|c seating plane gage plane 2 3 r1 r2 s c l1 a a2 a1 -|0.05 s 1 2 3

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